Here you can find a collection of electric and electronic circuits realized by the PSpice tool or by Cadence ORCAD Capture Lite. You can freely download, use or modify all the stuff you'll find here. Anyone who wishes to collaborate and share his experience, i invited to send, his works.
OrCAD 17.2 PSpice Designer Lite Software, it's freely downlonable, after registation, here
PSpice is a free open source software, download it here


ON-OFF BJT behaviour

To a BJT NPN and PNP BJT is applied to a sine voltage input; the BJTs go alternately in cut-off and saturation.


Shannon sampling theorem

PSpice proof of the Shannon sampling theorem

The signal is the sum of 4 sine voltages plus an offset, so in the spectrum we find 5 lines at 0Hz, 100Hz, 200Hz, 300Hz, 400Hz (in green in the second plot).
1) fs ≥ 2fmax
The spectrum of the sampled signal is the periodization of the original spectrum; fs=2kHz (in red). The alias are not overlaping because fc=2000Hz > 2fmax=2•400=800Hz. A low pass filter could reconstruct the original signal erasing lines over 400Hz.
1) fs < 2fmax
Now the alias are overlaping because fs=500Hz < 2fmax=2•400=800Hz. A low pass filter could not reconstruct the original signal.


Sample & Hold

Signal sampling by JFET

The clock opens and closes the FET. When the FET conducts, the capacitor reaches the "-prima-" voltage and follows it, When the FET doesn't conduct the capacitor holds the voltage. The first OP-AMP, due to his low output resistance guarantee a good independence from the load; the second OP-AMP, in buffer configuration, due to his high input resistance prevents the capacitor voltage loss.


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